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Date
02/27/07
06/18/07
Version
1.2
1.3
Revision
Changed document title and updated “Additional Documentation,” page 7 . Specified
FPGA device speed grade as "-1C ES". Updated “Initial Board Checks Before Applying
Power,” page 19 . Corrected board reference designator for Table 3-4, page 30 to use P1 as
PCI? Edge Connector pinout. Updated “DDR2 SDRAM SODIMM,” page 34 to
reference DDR2 reference design included with kit. Added lane assignments to
Table 3-20, page 58 . Added link to www.idt.com for availability of clock jitter attenuator
circuits on page 60 . Updated Table 3-33, page 80 to include ML555 support for plugging
board into 16-lane add-in card connector. Updated Table 3-37, page 86 to include
reference designs pre-loaded into ML555 Platform Flash devices. Add Note 3 to
Table 4-1, page 89 ; Slave SelectMAP not supported. Updated “SelectMAP Clock
Selection” including Table 4-7 and Figure 4-8 . Added reference to the Development
System Reference Guide for PROMGen and BitGen software applications. Updated
“Specifying the Xilinx PROM Device” including Figure 4-10 and Figure 4-13 . Added
Figure 4-14 and Figure 4-15 .
Updated Table 1-1, page 14 to clarify version and build information for PCI and PCI-X
IP cores. Revised Serial Bus Development section. Removed "ES" from FPGA part
number. Added footnote 3 to Table 3-3, page 27 . Updated Figure 3-8, page 55 and
Figure 3-9, page 56 to include a 4.7K Ω pull-up resistor on the SATA_MGT_CLKSEL
FPGA output and labeled the Clock MUX inputs. Defined the SATA_MGT_CLKSEL
default selection in Table 3-19, page 57 for FPGA output H15. Added additional text to
footnote 6 in Table 3-20, page 58 . Updated “Parallel Mode Operation,” page 62 to
indicate pressing and releasing of SW9 and SW11 to parallel load clock synthesizers after
power on to guarantee clock frequency. Updated Figure 3-14, page 76 and Table 3-34,
page 81 . Added footnote 1 to Table 4-5, page 95 . Updated “Generic Dynamic
Reconfiguration,” page 98 and “Platform Flash Image Generation and Programming,”
page 101 to include process steps and screen shots from ISE 9.1i. Inserted two new
figures ( Figure 4-11, page 105 and Figure 4-12, page 105 ).
UG201 (v1.4) March 10, 2008
www.xilinx.com
Virtex-5 FPGA ML555 Development Kit
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